| 摘要 |
A phase locking method and apparatus by which a phase of an input signal is locked using the input signal and a clock signal, where the phase locking method includes generating n multi-phase clock signals using the clock signal where n is an integer, generating n multi-phase input signals from the input signal corresponding to each of the n multi-phase clock signals, generating n error signals, that is, one for each of the n multi-phase input signals, extracting a low-frequency component from one of the generated n error signals or from a summation result of the generated n error signals, adding the extracted low-frequency component to each of the n error signals, and selecting one of the n error signals to which the low-frequency component is added in response to the clock signal and outputting the selected error signal used to generate the clock signal.
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