发明名称 SUBTRACTER
摘要 PURPOSE:To reduce a circuit scale by disposing an inversion circuit inverting respective bits of a subtrahend and executing the complementary conversion of '1', and full adders which set the carry output by means of the addition of the output value and a minuend to be a self carry input. CONSTITUTION:The inversion circuit 1 inverts respective bits of the subtrahend, executes complementary conversion of '1', and the full adders 2 add the output value of the circuit 1 and the minuend and set the carry output by addition to be the self carry input. An inversion selection circuit 3 outputs the output addition value of the adder 2 as an output when the carry output is '1', and inverts respective bits of the output addition value, inversely converts the comple ment of '1', and outputs it as a difference when the carry output is '0'. Name ly, 'end around carry' can be realized by setting the carry output of the adder 2 to be the self carry input since subtraction is attained by the complement conversion of '1' of the subtrahend.
申请公布号 JPH02292631(A) 申请公布日期 1990.12.04
申请号 JP19890112923 申请日期 1989.05.02
申请人 FUJITSU LTD 发明人 KUSUMOTO MASAYOSHI
分类号 G06F7/50;G06F7/507 主分类号 G06F7/50
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