| 摘要 |
A method and device are described for detecting bits in a read signal sampled at a system clock frequency which deviates from the bit frequency. A series of bit-frequency relevant signal values (B12) is computed from the series of system clock frequency-measured sample values (B1, B2, ...) as a convolution of the measured sample values having a function centered around the desired sampling instant, which function is the Fourier transform of a predetermined pulse response of the sampling procedure. This pulse response is chosen to be such that the sampling procedure is reliable for bit frequencies up to twice the system clock frequency. To be able to process such high bit frequencies in actual practice, a bit detector (320) according to the invention has two data outputs (321, 322) and one validity output (225). Whenever a computation has been finished, a pulse is supplied at the validity output whose frequency may be maximally equal to the system clock frequency. Per validity pulse, the bit detector can supply two sample values simultaneously at its two data outputs. |
