SYSTEM AND METHOD FOR OPTIMISING WORD WIDTHS OF DIGITAL CIRCUITS BY MEANS OF BIT-TRUE SIMULATIONS

摘要

Disclosed are a system and method for optimising word widths of digital circuits by means of bit-true simulations. The system comprises a model of the target circuit (5) with limiter circuits (7) that modify the value of the signals of which the word width is to be optimised, reducing the execution times of optimisation processes, without needing to reconfigure the PLD or emulate word widths by means of software instructions. Each limiter circuit (7) generates an output, limiting, at the logical level, the precision and/or effective range of the value of a piece of input data (NUM¡) according to a received instruction for controlling precision and/or effective range (10¡). The model of the target circuit (5) can be implemented in a hardware circuit of a PLD (2) or by means of software in a processor (8). Each limiter circuit (7) is normally located at the input and/or output of an arithmetic-logic operator (9) or arithmetic-logic unit (19).