Hybrid digital pulse width modulation (PWM) based on phases of a system clock

摘要

Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), trailing-edge-modulation (TEM), and/or dual-edge-modulation. An initial pulse may be generated based on a duty command, synchronous with the system clock, and may be registered with a D flip-flop under control of a selected phase of the system clock. Alternatively, a target count may be derived from the duty command, and an edge of the PWM pulse may be initiated when a count of the selected phase equals the target count. The pulse edge may be registered by a D flip-flop to a SR flip-flop under control of the selected phase. The phases of the system clock may be shared amongst multiple systems to generate multiple PWM signals. A system may include a DLL and digital logic, which may consist essentially of combinational logic and registers.

主权项

1. An apparatus, comprising, a first pulse width modulator and a controller to provide a first digital duty command to the first pulse width modulator, wherein the first digital duty command specifies a duty to within a fraction of a cycle of a system clock to the first pulse width modulator, and wherein the first pulse width modulator is configured to:
generate a first digital delay value based on a value of the first digital duty command and a maximum value of the first digital duty command; assert an edge of a pulse based on most significant bits of the first digital delay value; select a first one of multiple phases of the system clock based on least significant bits of the first digital delay value; and re-time the edge of the pulse based on the first selected phase of the system clock to adjust a width of the pulse.