| 摘要 |
<p>PURPOSE: To facilitate digital processing by comparing a delayed clock by an n-th stage delay circuit with a basic clock and generating a delay signal synchronously with the basic clock to control the delay. CONSTITUTION: A phase comparator circuit 21 compares a phase of a delayed clock Kn from an n-th stage delay circuit 1n with a phase of a basic clock and provides an output of a binary signal representing whether the phase of the delayed clock Kn is advanced or delayed more than the phase of the basic clock. When the phase of the delayed clock Kn is advanced more than the phase of the basic clock, a delay to increase the delay of delay control circuits 11-1n is fed respectively to the circuits 11-1n. When the phase of the delay clock Kn is delayed more than the phase of the basic clock, the circuit 31 provides a delay to reduce the delay of the circuits 11-1n to the circuits 11-1n. The delay of the circuits 11-1n is controlled uniformly by the circuit 31. Then a delayed clock Kn from the delay circuit in at the final stage is synchronously with the phase of the basic clock.</p> |
