FIELD EFFECT TRANSISTOR WITH A MULTILEVEL GATE ELECTRODE FOR INTEGRATION WITH A MULTILEVEL MEMORY DEVICE

摘要

A switching field effect transistor and the memory devices can be formed employing a same set of processing steps. An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures for memory devices and gate dielectric-channel structures for the field effect transistor can be simultaneously formed in a memory region and in a transistor region, respectively. After replacement of the sacrificial material layers with electrically conductive layers, portions of the electrically conductive layers in a memory region are electrically isolated from one another to provide independently controlled control gate electrodes for the memory devices, while portions of the electrically conductive layers in the transistor region are electrically shorted among one another to provide a single gate electrode for the switching field effect transistor.

主权项

1. A device comprising a field effect transistor, wherein the field effect transistor comprises:
a first vertical transistor channel portion extending through a first portion of an alternating stack of electrically conductive layers and insulating layers located over a substrate, wherein at least some of the electrically conductive layers are electrically shorted among one another to provide a gate electrode; a first gate dielectric laterally surrounding the first vertical transistor channel portion; a gate electrode contact structure extending through the first portion of the alternating stack and contacting at least some of the electrically conductive layers to electrically short at least some of the electrically conductive layers; a bottom active region located in, or on, the substrate and laterally spaced from the first vertical transistor channel portion; and a first top active region overlying the first vertical transistor channel portion, wherein one of the top and bottom active regions is a source region of the field effect transistor and another of the top and bottom active regions is a drain region of the field effect transistor.