| 发明名称 |
MULTI-LEVEL MEMORY APPARATUS AND DATA SENSING METHOD THEREOF |
| 摘要 |
A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal. |
| 申请公布号 |
US2016118115(A1) |
申请公布日期 |
2016.04.28 |
| 申请号 |
US201514746200 |
申请日期 |
2015.06.22 |
| 申请人 |
SK Hynix Inc. ;Korea Advanced Institute of Science and Technology |
发明人 |
RYU Seung Tak;KWON Ji Wook;JIN Dong Hwan |
| 分类号 |
G11C13/00 |
主分类号 |
G11C13/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A multi-level memory device comprising:
a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current; a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage; a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal; and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal. |
| 地址 |
Icheon KR |
