发明名称 Resistive random access memory and method for manufacturing the same
摘要 A resistive random access memory including a substrate, a dielectric layer disposed on the substrate and at least one memory cell string is provided. The memory cell string includes memory cells and second vias. The memory cells are vertically and adjacently disposed in the dielectric layer, and each of the memory cells includes a first via, two conductive lines respectively disposed at two sides of the first via and two variable resistance structures respectively disposed between the first via and the conductive lines. In the vertically adjacent two memory cells, the variable resistance structures of the upper memory cell and the variable resistance structures of the lower memory cell are isolated from each other. The second vias are respectively disposed in the dielectric layer under the first vias and connected to the first vias, and the vertically adjacent two first vias are connected by the second via.
申请公布号 US9305977(B1) 申请公布日期 2016.04.05
申请号 US201414583180 申请日期 2014.12.25
申请人 Powerchip Technology Corporation 发明人 Hsu Mao-Teng
分类号 H01L27/24;H01L45/00 主分类号 H01L27/24
代理机构 Jianq Chyun IP Office 代理人 Jianq Chyun IP Office
主权项 1. A resistive random access memory, comprising: a substrate; a dielectric layer, disposed on the substrate; and at least one memory cell string, comprising: a plurality of memory cells, vertically and adjacently disposed in the dielectric layer, wherein the memory cells comprise a plurality of first vias, a plurality of conductive lines and a plurality of variable resistance structures, and each of the memory cells comprises: a first via;two conductive lines, respectively disposed at two sides of the first via; andtwo variable resistance structures, respectively disposed between the first via and the conductive lines, whereinin the vertically adjacent two memory cells, the variable resistance structures of the upper memory cell and the variable resistance structures of the lower memory cell are isolated from each other; anda plurality of second vias, respectively disposed in the dielectric layer under the first vias and connected to the first vias, wherein the vertically adjacent two first vias are connected by one of the second vias.
地址 Hsinchu TW