发明名称 半導体装置
摘要 A semiconductor device includes a bit line connected to memory cells, a negative bias voltage generation circuit generating a negative bias voltage that is to be applied to the bit line during writing, and a negative bias reference voltage generation unit generating a negative bias reference voltage based on a resistance ratio between a first resistor and a second resistor.
申请公布号 JP5878837(B2) 申请公布日期 2016.03.08
申请号 JP20120152502 申请日期 2012.07.06
申请人 ルネサスエレクトロニクス株式会社 发明人 藤原 英弘
分类号 G11C11/413;G11C11/417 主分类号 G11C11/413
代理机构 代理人
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