| 发明名称 |
METHOD AND APPARATUS FOR CALCULATING DELAY TIMING VALUES FOR AN INTEGRATED CIRCUIT DESIGN |
| 摘要 |
A method and apparatus for calculating delay timing values for at least a part of an integrated circuit design. The method comprises applying a first Negative/Positive Bias Temperature Instability compensation margin to delay values for elements within the at least part of the IC design, identifying at least one lower-rate switching element within the at least part of the IC design, and applying at least one further, increased N/PBTI compensation margin to the delay value(s) for the at least one identified lower-rate switching element. |
| 申请公布号 |
US2015347653(A1) |
申请公布日期 |
2015.12.03 |
| 申请号 |
US201314759232 |
申请日期 |
2013.01.09 |
| 申请人 |
SOFER Sergey;BERKOVITZ Asher;PRIEL Michael |
发明人 |
SOFER SERGEY;BERKOVITZ ASHER;PRIEL MICHAEL |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of calculating delay timing values for at least a part of an integrated circuit, IC, design, the method comprising:
applying a first Negative/Positive Bias Temperature Instability, N/PBTI, compensation margin to delay values for elements within the at least part of the IC design; identifying at least one lower-rate switching element within the at least part of the IC design; and applying at least one further, increased N/PBTI compensation margin to the delay value(s) for the at least one identified lower-rate switching element. |
| 地址 |
Rishon Lezion IL |
