Continuously adaptive phase locked loop synthesizer

摘要

A continuously adaptive phase locked loop synthesizer is disclosed in which error correction pulses from a phase detector are separated into narrow pulse width and wide pulse width pulses. The wide pulse width pulses are coupled to the loop filter to enable a rapid charge of the loop filter to provide a VCO control voltage on a control line connected to the output of the loop filter. The narrow pulse width pulses are filtered by a narrow bandwidth filter before being applied to the loop filter thus enabling a slow charge of the loop filter. The narrow bandwidth filter is decoupled from the control line but referenced to the control line voltage.