CMOS FABRICATION

摘要

A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

主权项

1. A process for forming a memory device, the process comprising:
patterning gates in nMOS and pMOS regions for CMOS circuits; masking the pMOS regions with a first mask; conducting source/drain doping and supplemental doping between source/drain regions and the gates in the nMOS regions while the pMOS regions remain masked with the first mask; masking the nMOS regions with a second mask; and conducting source/drain doping and supplemental doping between source drain regions and the gates in the pMOS regions while the nMOS regions remain masked with the second mask.