发明名称 Method of Forming Wafer-Level Molded Structure for Package Assembly
摘要 A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.
申请公布号 US2014206140(A1) 申请公布日期 2014.07.24
申请号 US201414224921 申请日期 2014.03.25
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 Wang Tsung-Ding;Lee Bo-I;Lee Chien-Hsun
分类号 H01L23/00 主分类号 H01L23/00
代理机构 代理人
主权项 1. A method of forming an integrated circuit structure, the method comprising: bonding top dies onto a bottom wafer; molding a first molding material onto and in between the top dies and the bottom wafer; sawing the bottom wafer, the top dies and the first molding material to form molding units, wherein each of the molding units comprises one of the top dies and a bottom die sawed from the bottom wafer; bonding one of the molding units onto a package substrate; molding a second molding material onto the one of the molding units and the package substrate; and sawing the package substrate and the second molding material to form package-molded units.
地址 Hsin-Chu TW