DEVICE AND METHOD FOR PERFORMING TIMING ANALYSIS

摘要

A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.

主权项

1. A device for performing timing analysis used in a programmable logic array system comprising:
a plurality of first basic I/O terminals to receive a plurality of under-test signals from an under-test unit; a plurality of second basic I/O terminals; a channel multiplexer to receive the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals; a plurality of high-speed I/O terminals having a logic level analyzing speed higher than that of the first and second basic I/O terminals, wherein the high-speed I/O terminals are connected to the second basic I/O terminals; a sampling module to receive the group of under-test signals outputted from the second basic I/O terminals through the high-speed I/O terminals and to sample the group of under-test signals to generate a sample result; and a timing analysis module to perform a timing analysis and measurement according to the sample result.