发明名称 WAFER LEVEL PACKAGE STRUCTURE AND MANUFACTURING METHOD OF THE SAME
摘要 The present invention provides a semiconductor package structure, which includes a die, a plurality of bonding wires, an encapsulant, and a plurality of first external terminals. The die has an active surface and a back surface. A first end of each of the bonding wires is connected to the back surface of the die, and a second end opposite to the first end is electrically connected to the active surface of the die. The encapsulant covers the back surface of the die and the bonding wires, wherein a portion of each of the bonding wires is exposed from the encapsulant. The first external terminals are disposed on the top surface of the encapsulant, and cover the exposed portions of the bonding wires respectively and are electrically connected to the bonding wires.
申请公布号 US2014061899(A1) 申请公布日期 2014.03.06
申请号 US201313846608 申请日期 2013.03.18
申请人 CHIPMOS TECHNOLOGIES INC 发明人 LIAO TSUNG JEN
分类号 H01L23/498;H01L23/00 主分类号 H01L23/498
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