| 摘要 |
Embodiments of the disclosed technology use high-speed interpolated (interdigitated) sampling for the specific purpose of GPR (Ground-Penetrating RADAR). This technology solves several issues associated with high-speed sampling in GPR which included 1) dynamic range limitations, 2) regulatory compliance issues, 3) sampler core offset error, and 4) timing errors. High-speed interpolated sampling GPR is implemented using a high-speed ADC in combination with trigger logic (such as an FPGA) and a programmable delay generator. The FPGA or other trigger logic generates a series of randomly dithered trigger pulses. A variable delay generator (or "Vernier") is synchronously controlled in order to produce the fractional timing. The timing of the pulses is randomly or pseudo-randomly dithered, and the phase of the interpolation is shuffled in order to avoid producing discrete spectral lines in the radiated RADAR signal. |
