发明名称 POWER SAVING TECHNIQUES THAT USE A LOWER BOUND ON BIT ERRORS
摘要 A read back bit sequence and charge constraint information are obtained. A lower bound on a number of bit errors associated with the read back bit sequence is determined based at least in part on the read back bit sequence and the charge constraint information. The lower bound and an error correction capability threshold associated with an error correction decoder are compared. In the event the lower bound is greater than or equal to the error correction capability threshold, an error correction decoding failure is predicted and in response to the prediction a component is configured to save power.
申请公布号 US2014013166(A1) 申请公布日期 2014.01.09
申请号 US201313902410 申请日期 2013.05.24
申请人 SK HYNIX MEMORY SOLUTIONS INC. 发明人 SUBRAMANIAN ARUNKUMAR;LEE FREDERICK K.H.;BELLORADO JASON;TANG XIANGYU;ZENG LINGQI
分类号 G06F1/32 主分类号 G06F1/32
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