IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS MINIMIZING HARDWARE/FIRMWARE INTERACTIONS

摘要

A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.