发明名称 AUTOMATIC-LAYING WIRING DEVICE AND AUTOMATIC-LAYING WIRING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide an automatic-laying wiring device allowing reduction in working man-hours and reduction in the size of a lay-out area by virtue of automatic design of a semiconductor device having plural power-supply voltages. <P>SOLUTION: A processing part extracts (step 16) plural wiring paths interconnecting plural cells from a result of an automatic layout, the wiring paths connecting from cells within a first power domain to those within a second power domain. The processing part performs the steps of: extracting (17) power source-active information for each operation mode of the first and second power domains; extracting (18) a third power domain being active when the first and second power domains are active; inserting (19) an additional cell into the third power domain for resolving nonconformity to a specification item of a specific cell; and wiring (22) between the specific cell within the first power domain and the specific cell within the second power domain cell via the additional cell. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012203632(A) 申请公布日期 2012.10.22
申请号 JP20110067382 申请日期 2011.03.25
申请人 RENESAS ELECTRONICS CORP 发明人 TAMAI NORIYUKI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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