发明名称 |
HIERARCHICAL BUFFERED SEGMENTED BIT-LINES BASED SRAM |
摘要 |
A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line. |
申请公布号 |
US2011305099(A1) |
申请公布日期 |
2011.12.15 |
申请号 |
US201113105806 |
申请日期 |
2011.05.11 |
申请人 |
SHARMA VIBHU;COSEMANS STEFAN;DEHAENE WIM;CATTHOOR FRANCKY;ASHOUEI MARYAM;HUISKEN JOS;STICHTING IMEC NEDERLAND;KATHOLIEKE UNIVERSITEIT LEUVEN;IMEC |
发明人 |
SHARMA VIBHU;COSEMANS STEFAN;DEHAENE WIM;CATTHOOR FRANCKY;ASHOUEI MARYAM;HUISKEN JOS |
分类号 |
G11C7/12 |
主分类号 |
G11C7/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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