发明名称 |
METHODS AND APPARATUSES FOR CORDIC PROCESSING |
摘要 |
A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.
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申请公布号 |
US2011225222(A1) |
申请公布日期 |
2011.09.15 |
申请号 |
US20100724302 |
申请日期 |
2010.03.15 |
申请人 |
INTEGRATED DEVICE TECHNOLOGY, INC. |
发明人 |
GUNWANI MANOJ;VERMA HAREKRISHNA |
分类号 |
G06F17/16;G06F5/01 |
主分类号 |
G06F17/16 |
代理机构 |
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地址 |
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