发明名称 |
Test pad design for reducing the effect of contact resistances |
摘要 |
An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.
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申请公布号 |
US7825678(B2) |
申请公布日期 |
2010.11.02 |
申请号 |
US20080196531 |
申请日期 |
2008.08.22 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
DOONG YIH-YUH;LO TSENG CHIN;LEE CHIEN-CHANG;SHAO CHIH-CHIEH |
分类号 |
G01R31/02 |
主分类号 |
G01R31/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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