| 摘要 |
A 3D-IC verification method is disclosed. Alignment mark(s), through-silicon via (TSV) and bump structure are defined on dummy layer(s) for each level of the 3D IC, followed by verifying chip(s), the alignment mark, the TSV and the bump structure for each level respectively. The dummy layers of the levels are extracted, and are then integrated. The integrated dummy layers of the 3D IC are then verified vertically.
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