| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a parasitic capacitance between a wiring layer and a semiconductor board without forming a hollow structure in a wiring region outside a protection cap. Ž<P>SOLUTION: A thick insulation layer 17a arranged between signal lines 15a, 15b and a thick insulation layer 17b arranged between signal lines 15b, 15c are formed on the outside of a protection cap 20, and signal lines 18a, 18b are formed so that the whole exposed faces of the thick insulation layers 17a, 17b are covered. Then, the signal line 18a is connected to the signal lines 15a, 15b, and the signal line 18b is connected to the signal lines 15b, 15c. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
|
