发明名称 BIT GENERATOR
摘要 A system comprising a feedback shift-register having L serially connected stages, and a non-linear feedback sub-system to receive input from stage n and 2n+1, and including a first AND gate having a first and second input operationally connected to the output of stage n and 2n+1, respectively, the sub-system having an output based on a value of an output of the first AND gate, a bit generator operative to generate bits, and an XOR gate having a first and second input, an output of the bit generator being operationally connected to the first input of the XOR gate, the output of the sub-system being operationally connected to the second input of the XOR gate, the output of the XOR gate being operationally connected to the input of the first stage of the shift-register. Related apparatus and methods are also described.
申请公布号 US2010036899(A1) 申请公布日期 2010.02.11
申请号 US20080448663 申请日期 2008.06.26
申请人 KALUZHNY URI 发明人 KALUZHNY URI
分类号 G06F7/58;G11C19/00 主分类号 G06F7/58
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