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发明名称
Clock-edge modulated serial link with DC balance control
摘要
申请公布号
EP1780930(A3)
申请公布日期
2009.12.23
申请号
EP20060255352
申请日期
2006.10.18
申请人
SILICON IMAGE, INC.
发明人
KIM, GYUDONG;CHOE, WON JUN;JEONG, DEOG-KYOON;KIM, JAEHA;LEE, BONG-JOON;KIM, MIN-KYU
分类号
H04L7/00;H04L25/49
主分类号
H04L7/00
代理机构
代理人
主权项
地址
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