发明名称 SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE
摘要 Provided is a semiconductor chip, which has a number of electrodes reduced as much as possible, eliminates a connection failure by maintaining parallelism with a mounting substrate at the time of mounting and suppresses even breakage of a semiconductor circuit. In the semiconductor chip, for instance, a cross-shaped connecting bump arrangement region (23) is formed between memory banks (22A-22D) facing each other with a prescribed space in etween. In a region (23A) in the cross-shaped connecting bump arrangement region (23), a group of signal input/output connecting bumps (21A) (first electrodes) are arranged. In a region (23B) which orthogonally intersects with a region (23A) wherein the group of signal input/output connecting bumps (21A) are formed, a group of power/grounding connecting bumps (21B) are arranged. Thus, when a storage device chip (20) is mounted on a wiring chip (10), a tilt of the storage device chip (20) is supported by the power/grounding connecting bumps (21B) (through a solder), and parallelism is maintained by the minimum number of bumps. In such manner, for instance, a storage chip (20) is constituted.
申请公布号 WO2009104536(A1) 申请公布日期 2009.08.27
申请号 WO2009JP52493 申请日期 2009.02.16
申请人 LIQUID DESIGN SYSTEMS, INC.;MABUCHI, YOSHIHIRO 发明人 MABUCHI, YOSHIHIRO
分类号 H01L21/822;H01L21/60;H01L25/04;H01L25/065;H01L25/07;H01L25/18;H01L27/04 主分类号 H01L21/822
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