| 摘要 |
A clock synchronization circuit and a clock synchronization method which generate an internal clock synchronized to an external clock is presented. The circuit and method include a clock enable control circuit generating a clock enable control signal controlled by a power supply voltage and a power-down signal. The circuit and method also include a clock generating circuit receiving an input clock which selectively generates an internal clock synchronized to an external clock using the input clock using the clock enable control signal. Whereupon, a locking failure can be prevented by performing a phase update operation selectively in accordance with whether the power supply voltage is varied or not in the power-down mode. Furthermore, current consumption can be reduced by controlling phase update time in accordance with a variable magnitude of the power supply voltage.
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