发明名称 Method of implementing polishing uniformity and modifying layout data
摘要 A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.
申请公布号 US7322014(B2) 申请公布日期 2008.01.22
申请号 US20060555314 申请日期 2006.11.01
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 TRAVIS EDWARD O.;ALDRICH NATHAN A.;TIAN RUIQI
分类号 G06F17/50;H01L21/302;H01L21/321 主分类号 G06F17/50
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