发明名称 |
Method and apparatus for determining optimum initial value for test pattern generator |
摘要 |
The purpose of the invention is to determine an optimum initial value to be input to a test pattern generator in order to achieve efficient testing of an integrated circuit. To achieve this purpose, a minimum test length is obtained by performing a fault simulation and a reverse-order fault simulation using an arbitrarily given initial value; the next initial value that is likely to yield a test length shorter than the minimum test length is computed and a fault simulation is performed using the thus computed initial value; and the next initial value that is likely to yield a test length shorter than that test length is computed and a fault simulation is performed using the thus computed initial value. By repeating this process, an initial value that yields the shortest test length is obtained.
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申请公布号 |
US7299394(B2) |
申请公布日期 |
2007.11.20 |
申请号 |
US20030400911 |
申请日期 |
2003.03.28 |
申请人 |
SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER |
发明人 |
ICHINO KEN-ICHI;ARAI MASAYUKI;FUKUMOTO SATOSHI;IWASAKI KAZUHIKO;SHODA TAKESHI;SATO MASAYUKI |
分类号 |
G01R31/28;G01R31/3183;G06F11/26;G06F17/50 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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