| 摘要 |
A parallel compression test apparatus of a memory apparatus is provided to detect fail of a memory cell by compressing data of plural bits having various logic levels. Compression units compress N-bit data(IN1-IN4). A compression unit(204) compresses the N-bit data. A compression unit(205) compresses the N-bit data. The compression units are comprised of an AND gate(201), a NOR gate(202), and an OR gate(203). The AND gate receives the N-bit data. The NOR gate receives the N bit data. The OR gate receives an output signal of the AND gate an output signal of the NOR gate. The compression unit is an OR gate receiving the N-bit data. The compression unit is an AND gate receiving the N-bit data. The output of the OR gate which is the output of the compression unit is outputted to a data pin(Q) through a switch(207) when a control signal(TM1) is a high level. The output of the OR gate, which is the output of the compression unit, is outputted to the data pin through a switch(209) when a control signal(TM2) is a high level. The output of the OR gate, which is the output of the compression unit, is outputted to the data pin through a switch(211) when a control signal(TM3) is a high level.
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