DUAL LAYER BUS ARCHITECTURE FOR SYSTEM-ON-A-CHIP

摘要

PROBLEM TO BE SOLVED: To provide an effective bus architecture for reducing the amount of main system bus bandwidth to be consumed by various multimedia processing procedures.

SOLUTION: The bus architecture comprises a main bus designed and adapted to connect a microprocessor, an image capture module, and a dual master module to a high density memory and a secondary bus operating independently of the main bus and designed and adapted to connect the dual master module to a high-speed secondary memory.

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