发明名称 STANDBY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a standby circuit for decreasing a delay time from an input of an external trigger until an amplitude of a voltage applied to a load L starts changing. SOLUTION: The standby circuit comprises: an amplifier 34 including a push-pull output stage comprising MOS transistors 32, 33 and driving the MOS transistors 32, 33; a control level control circuit 2 for applying voltage limit to an input signal to the amplifier 34; an integration unit 1 for generating an input signal to the limit level control circuit 2; and a voltage limit circuit 4 for applying a limit to a signal generated from the integration unit 1 to a constant voltage width when an external trigger starts producing the signal, when the external trigger is received, the voltage limit circuit 4 applies voltage limit to an output of the integration unit 1 to a value at which the voltage applied to the load L starts changing, so that a time difference from the input of the external trigger until the amplitude of the voltage applied to the load L starts decreasing is reduced. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006050199(A) 申请公布日期 2006.02.16
申请号 JP20040227748 申请日期 2004.08.04
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KUME TOMOHIRO;SATO TAKAAKI
分类号 H03K17/687 主分类号 H03K17/687
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