发明名称 |
Method and apparatus for reducing leakage current in a read only memory device using transistor bias |
摘要 |
A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by applying a biased gate voltage (relative to a source voltage) to the gate of at least one of transistor in the array. The biased gate voltage is applied at least during a precharge phase of a read cycle. When the array transistors are n-channel transistors, the biased voltage is a negative bias voltage (relative to the source voltage). When the array transistors are p-channel transistors, the biased voltage is a positive bias voltage (relative to the source voltage). Applying a negative backgate bias to the transistor's p-well contact can also reduce n-channel transistor subthreshold leakage current. Thus, for an n-channel array, a negative gate voltage and backgate bias (optional) are applied to cell transistors in the off state. Similarly, the subthreshold leakage current of p-channel transistors is reduced by applying a more positive gate-to-source bias and a positive n-well-to-source bias.
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申请公布号 |
US2005162941(A1) |
申请公布日期 |
2005.07.28 |
申请号 |
US20040764000 |
申请日期 |
2004.01.23 |
申请人 |
DUDECK DENNIS E.;EVANS DONALD A.;KOHLER ROSS A.;MCPARTLAND RICHARD J.;PHAM HAI Q. |
发明人 |
DUDECK DENNIS E.;EVANS DONALD A.;KOHLER ROSS A.;MCPARTLAND RICHARD J.;PHAM HAI Q. |
分类号 |
G11C7/12;G11C17/00;G11C17/12;(IPC1-7):G11C17/00 |
主分类号 |
G11C7/12 |
代理机构 |
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主权项 |
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地址 |
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