| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can test an internal memory at high speed by using a PLL prepared inside by an external clock from an external low speed tester. SOLUTION: A test I/O data control circuit 1-2 is synchronized with a clock signal and performs writing and reading of test data to/from a memory cell included in a memory core 1-1. Test data input time series compression circuit 1-3 has a flag register, a data register and a computing unit. The flag register stores a plurality of flag data, and the data register stores a first test data inputted corresponding to the command input. An arithmetic circuit performs operation of the flag data stored in the flag register with a first test data stored in the data register for each cycle from the input time of the first test data to the plurality of number of cycles of the clock signal, and the data control circuit 1-2 generates test data to be written in the memory cell. COPYRIGHT: (C)2005,JPO&NCIPI
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