发明名称 |
DATA PROCESSOR |
摘要 |
PURPOSE: To remove a sorting and merging task function from a central processing unit(CPU) by searching a vector register in a vector processor in order to execute tournament tree merging and sorting. CONSTITUTION: A tree sort having a hardware logic node register, an output selector and a comparator attains sorting/merging operation based upon a vector processor. Traffic between plural storage means can be sharply reduced by executing a hardware tree and an updating logic circuit 302 by the vector processor. A vector register 304 provides input data to hardware tree structure concerned. Multivector counting and multivector interrupting index (VIX) operation, string length and a merging mask are used relationally to a vetor merging instruction. A vector merging forms a new code word at the time of outputting a code word with an equal compared result. |
申请公布号 |
JPH04247571(A) |
申请公布日期 |
1992.09.03 |
申请号 |
JP19910229422 |
申请日期 |
1991.08.15 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
RESURII CHIYAARUZU GARUSHIA;DEBITSUDO BURUUSU RINDOKUISUTO;JIERARUDO FURANKURIN ROURO |
分类号 |
G06F7/24;G06F7/36;G06F15/78;G06F17/30 |
主分类号 |
G06F7/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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