发明名称 PROCESSING ARCHITECTURE FOR A RECONFIGURABLE ARITHMETIC NODE IN AN ADAPTIVE COMPUTING SYSTEM
摘要 A computational unit, or node, in an adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types include the following: Asymmetric FIR Filter, Symmetric FIR Filter, Complex Multiply / FIR Filter, Sum-of-absolute-differences, Bi-linear Interpolation, Biquad IIR Filter, Radix-2 FFT/IFFT, Radix-2 DCT/IDCT, Golay Correlator, Local Oscillator / Mixer.
申请公布号 WO2004107201(A2) 申请公布日期 2004.12.09
申请号 WO2003US37225 申请日期 2003.11.19
申请人 QUICKSILVER TECHNOLOGY, INC. 发明人 SCHEUERMANN, W., JAMES
分类号 G06F15/78;G06F17/14 主分类号 G06F15/78
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