| 摘要 |
A DLL circuit which can prevent transition to a pseudo lock state is provided. The DLL circuit includes a delay stage 11 to which a reference clock is input and in which variable delay elements D being able to change an amount of delay are connected in a plurality of stages, a phase comparator (PH Comp) 14 which compares the phase of the reference clock to the phase of one delay signal extracted from the delay stage, and a delay control circuit 12 which performs delay control of the delay element in the delay stage on the basis of the comparison result by the phase-comparison means, and DFF 15 which detects a phase relationship of at least two delay signals extracted from the delay stage to discriminate a state which is not a normal lock state and controls the delay control circuit to perform state transition to the normal lock state.
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