发明名称 |
LOCKING LOOP CIRCUIT FOR BLOCKING ABRUPT JITTER INFORMATION AND BLOCKING METHOD THEREOF |
摘要 |
<p>PURPOSE: A locking loop circuit for blocking abrupt jitter information and a blocking method thereof are provided to reduce a jitter of an output clock signal by blocking an abrupt jitter due to abrupt power noise or an abrupt jitter due to an influence of a system board. CONSTITUTION: A locking loop circuit for blocking abrupt jitter information includes a phase detector, a locking circuit, and an abrupt jitter information blocking circuit. The phase detector(51) is used for detecting a phase difference between an input signal and a feedback clock signal. The locking circuit(53) is used for generating the feedback clock signal in response to an output signal of the phase detector. The abrupt jitter information blocking circuit(55) is used for comparing the phase difference with a predetermined phase window and generating a halt signal according to a compared result.</p> |
申请公布号 |
KR20040064758(A) |
申请公布日期 |
2004.07.21 |
申请号 |
KR20030001593 |
申请日期 |
2003.01.10 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE, JONG SU |
分类号 |
G11C7/22;G11C8/00;G11C11/4076;H01L27/00;H03K5/00;H03K5/13;H03K5/131;H03K17/00;H03K17/687;H03L7/06;H03L7/081;H03L7/089;H03L7/095;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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