| 摘要 |
PURPOSE: A method for manufacturing a semiconductor device is provided to improve topology and to prevent damage of a via hole and an interlayer dielectric by filling the via hole of a dual damascene pattern using an SOG(Spin On Glass) layer. CONSTITUTION: A barrier layer(12), an interlayer dielectric(14) and a passivation layer(16) are sequentially deposited on a substrate(10). A via hole is formed by patterning the passivation layer and the interlayer dielectric. An SOG layer(20) is coated to fill the via hole. A trench(26) with a relatively wide width is formed by patterning the SOG layer and the passivation layer. The remaining SOG layer is wet-etched. A metal interconnection of a dual damascene structure is formed by filling metal in the via hole and the trench.
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