PRIVATE CACHE MISS AND ACCESS MANAGEMENT IN A MULTIPROCESSOR SYSTEM WITH SHARED MEMORY

摘要

Computer system including group of CPUs (22), and CPU bus (10) coupled to a private caches in the CPUs (22) and to shared cache (11). Each private cache includes a cache controller having a processor directory (31) for identifying information blocks resident in cache memory (40), a cache miss output buffer (32) for storing the identifications of blocks to be swapped out of cache memory (40), a cache miss input buffer stack (35) for storing the identifications of all blocks to be swapped out from all the CPUs (22), a comparator (34) for comparing the identifications in the cache miss output buffer stack (32) with the identifications in the cache miss input buffer stack (35) and control logic, that responsive to the comparator (34) sensing a compare inhibits the broadcast of a swap operation onto the CPU bus (10) and converts the swap operation into a "siphon" operation to the requesting CPU.