发明名称 |
Method of forming an alignment feature in or on a multi-layered semiconductor structure |
摘要 |
A method of forming a multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
|
申请公布号 |
US6706609(B2) |
申请公布日期 |
2004.03.16 |
申请号 |
US20010867202 |
申请日期 |
2001.05.29 |
申请人 |
AGERE SYSTEMS INC.;ELITH, LLC |
发明人 |
BOULIN DAVID M.;FARROW REGINALD C.;KIZILYALLI ISIK C.;LAYADI NACE;MKRTCHYAN MASIS |
分类号 |
G03F7/20;G03F9/00;H01J37/304;H01J37/305;H01L21/027;H01L23/544;(IPC1-7):H01L21/308 |
主分类号 |
G03F7/20 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|