Anordnung zum willkürlichen Abtasten von Instruktionen in einer Prozessorpipeline
摘要
An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information. <IMAGE>
申请公布号
DE69819849(D1)
申请公布日期
2003.12.24
申请号
DE1998619849
申请日期
1998.11.25
申请人
COMPAQ COMPUTER CORP., HOUSTON
发明人
CHRYSOS, GEORGE Z.;DEAN, JEFFREY A.;HICKS, JAMES E.;LEIBHOLZ, DANIEL L.;MCLELLAN, EDWARD J.;WALDSPURGER, CARL A.;WEIHL, WILLIAM E.