| 摘要 |
PROBLEM TO BE SOLVED: To increase a withstanding voltage of a triple well without increasing a threshold voltage of a MOS transistor formed in the triple well. SOLUTION: A semiconductor device comprises the triple well wherein a deep N well 3 is formed in a P substrate 1 and an IP well 5 is formed in the deep N well 3, and an N+ diffusion layer formed in the IP well 5. An impurity profile of the deep N well 3 comprises a first impurity profile 13a having a deep junction depth, and a second impurity profile 13b which has a peak concentration for an N-type impurity higher than that in the first impurity profile 13a and has a shallow junction depth. A position of depth of an inflection point between the first impurity profile 13a and the second impurity profile 13b is formed at a position shallower than the deepest position of an impurity profile 15 of the IP well 5. COPYRIGHT: (C)2004,JPO
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