发明名称 |
Precision-controlled duty cycle clock circuit |
摘要 |
A clock signal duty cycle control circuit is provided that receives an incoming signal from a clock signal input source and generates an improved output clock signal having an accurately controlled duty cycle. The circuit controls the duty cycle of the output clock signal by comparing the incoming signal to a reference value in a comparator. The reference value is derived from a reference charge stored on a capacitor. The reference charge is built up in the capacitor using the currents from a current source and a current sink, which are controlled using translated output signals from the comparator.
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申请公布号 |
US2003193357(A1) |
申请公布日期 |
2003.10.16 |
申请号 |
US20030442916 |
申请日期 |
2003.05.21 |
申请人 |
WYNEN JOHN;MADTER RICHARD;FERGUSSON ANDREW |
发明人 |
WYNEN JOHN;MADTER RICHARD;FERGUSSON ANDREW |
分类号 |
H03K5/156;(IPC1-7):H03K3/017 |
主分类号 |
H03K5/156 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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