| 摘要 |
PURPOSE: A decoding circuit is provided to improve the operational speed of the decoding circuit by reducing the number of stages of the logic gates in comparison with the conventional decoding circuit. CONSTITUTION: A decoding circuit(200) includes a plurality of inverters(202a,202b,202c), a plurality of NOR gates(204a-204h), a plurality of AND gates(206a-206h), a plurality of NOR gates(208a-208h), a plurality of inverters(210a-210h) and a first and a second inverters(212,214). The inverters(202a,202b,202c) convert the address signals(BX3-BX5) and supply the inverted address signals(BX3-BX5) to the corresponding NOR gates(204A-204h). The inverter(202a) inverts the address signal(BX3), the inverter(202b) inverts the address signal(BX4) and the inverter(202c) inverts the address signal(BX4).
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