发明名称 |
Programmable network architecture |
摘要 |
An apparatus capable of testing a plurality of JTAG compliant integrated circuits where at least one of the integrated circuits includes an enhanced embedded debug module is described. The apparatus is capable of selectively testing certain of the integrated circuits located at specified locations. In this way, integrated circuits included in a target device having defective or missing integrated circuits can still be tested. The apparatus also allows access to enhanced JTAG debug protocol within a mixed IC (OCDS and non-OCDS) network. |
申请公布号 |
GB2344430(B) |
申请公布日期 |
2003.05.07 |
申请号 |
GB19990025586 |
申请日期 |
1999.10.28 |
申请人 |
* INFINEON TECHNOLOGIES CORPORATION |
发明人 |
OLIVIER * GARREAU |
分类号 |
G06F11/22;G01R31/28;G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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