| 摘要 |
PROBLEM TO BE SOLVED: To simplify a manufacturing process of CSP and to make the chip size smaller. SOLUTION: A first metal wiring layer 7 that consists of an Al alloy layer is formed on a first interlayer insulating layer 5. A second interlayer insulating layer 15 consists of a PSG film 9, an SiN film 11 and a photosensitive polyimide layer 13, and has a through hole 17 on the first metal wiring layer 7. A second metal wiring layer 19 that consists of the Al alloy layer and a land area 21 are formed. A sealing layer 29 consists of a PSG film 23, an SiN film 25 and a photosensitive polyimide layer 27, and has an opening 31 on the land area 21. Since the second metal wiring layer 19 and the sealing layer 29 are formed in a wafer process and a wafer test may be performed only once after a solder ball 35 is mounted, the manufacturing process is simplified. Further, the first metal wiring layer 7 is not provided with a metal electrode pad for the wafer test as in prior arts, it is possible to make the chip area smaller.
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