发明名称 OUTPUT BUFFER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an output buffer circuit with which a noise can be reduced by suppressing the rapid change of an output current without increasing production costs. SOLUTION: A body voltage control circuit 17 is provided for controlling the body voltages of a PMOS output transistor 11a and an NMOS output transistor 11b, the input signal of an input line 12 is detected when switching output from a high level to a low level, a voltage equal to or lower than the source voltage of the NMOS output transistor 11b is impressed to the body of the NMOS output transistor 11b, and the threshold voltage of the NMOS output transistor 11b is increased rather than the voltage before the impression of the voltage equal to or lower than the source voltage. Besides, the input signal of the input line 12 is detected when switching the output from the low level to the high level, a voltage equal to or higher than the source voltage of the PMOS output transistor 11a is impressed to the body of the PMOS output transistor 11a, the threshold voltage of the PMOS output transistor 11a is decreased rather than the voltage before the impression of the voltage equal to or higher than the source voltage, the peak value of a charging/discharging current is suppressed and noises on a GND line and a power supply line are reduced.
申请公布号 JP2003023348(A) 申请公布日期 2003.01.24
申请号 JP20010209366 申请日期 2001.07.10
申请人 SHARP CORP 发明人 KAMAYA KEIZO
分类号 H03K19/0175;(IPC1-7):H03K19/017 主分类号 H03K19/0175
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